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dual, current - output, serial - input, 16 - /14 - bit dacs data sheet ad5545 / ad5555 rev. g document feedback information furnished by analog devices is believe d to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no lice nse is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781. 329.4700 ? 2003 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 16- bit resolution ad5545 14- bit resolution ad5555 1 lsb dnl monotonic 1 lsb inl 2 ma full - scale current 20%, with v ref = 10 v 0.5 s settling time 2q multiplying reference - input 6.9 mhz bw zero or midscale power - up preset zero or midscale dynam ic reset 3 - wire interface compact 16 - lead tssop package applications automatic test equipment instrumentation digitally controlled calibration industrial control plcs programmable attenuator product overview the ad5545/ad5555 are 16 - bit/14 - bit, current - o utput, digital - to - analog converters designed to operate from a 4.5 v to 5 .5 v su p ply range . an external reference is needed to establish the full - scale ou t put - current. an internal feedback resistor (r fb ) enhances the resistance and temperature tracking w hen combined with an external op amp to complete the i - to - v conversion. a serial data interface offers high speed, 3 - wire microcontroller compatible inputs using serial data in (sdi), clock (clk), and chip select ( cs ). additional ldac function allows simultaneous update operation. the internal reset logic allows power - on preset and dynamic reset at either zero or midscale, depen d ing on the state of the msb pin. the ad5545/ad5555 are packaged in the compact tssop - 16 pack age and can be operated from ? 40c to +85c. functional block dia gram ad5545/ ad5555 v dd r fb a v ref b v ref a i out a a gnd a sdi cs clk dgnd msb rs ldac dac a dac a b d0..dx en r r r r 16 or 14 addr decode input register power- on reset input register dac a register dac b register r fb b i out b a gnd b dac b 0 2 9 1 8 - 0 - 0 0 1 figure 1.
ad5545/ad5555 data sheet rev. g | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 product overview ............................................................................. 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 timing diagrams .......................................................................... 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and func tion descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 9 digital - to - analog converter ...................................................... 9 serial data interface ................................................................... 10 power - up sequence ................................................................... 11 layout and power supply bypassing ....................................... 11 grounding ................................................................................... 11 applications information .............................................................. 12 stability ........................................................................................ 12 positive voltage output ............................................................. 12 bipolar output ............................................................................ 12 programmable current source ................................................ 13 dac with programmable input reference range ................ 14 reference sel ection .................................................................... 15 amplifier selection .................................................................... 15 evaluation board for the ad5545 ................................................ 17 system demonstration platform .............................................. 17 operating the evaluation board .............................................. 17 evaluation board schematics ................................................... 18 evaluation board layout ........................................................... 21 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 4 /1 3 rev. f to rev. g change s to product overview section .......................................... 1 changes to ordering guide .......................................................... 23 2 /1 3 rev. e to rev. f change to v dd pin description, table 3 ........................................ 6 changed ada4899 to ada4899 - 1, table 12 ............................. 16 changes to ordering guide .......................................................... 23 1 2 /1 1 rev. d to rev. e added figure 13 ; renumbered sequentially ................................ 8 5/11 rev. c to rev. d added evaluation board for the ad5545 section, system demonstration platform section, and operating the evaluation board section .................................................................................. 1 7 added figure 2 5 and figure 2 6 ; renumbere d sequentially ..... 17 added evaluation board schematics section, figure 2 7 .......... 18 added figure 2 8 .............................................................................. 19 added figure 29 .............................................................................. 20 added evaluation board layout section, figure 3 0 , and figure 3 1 , ......................................................................................... 21 added figure 3 2 .............................................................................. 22 changes to ordering guide .......................................................... 2 3 3 /11 rev. b to rev. c cha nge to equation 4, bipolar output section .......................... 12 4 /10 rev. a to rev. b changes to 2q multiplying reference input ................................. 1 changes to ac characteristics and endnote 3 in table 1 ........... 4 changes to figure 13 and figure 15 ............................................... 8 added reference selection section, amplifier select ion section, and table 10 .................................................................................... 15 added table 11 and table 12 ........................................................ 16 changes to ordering guide .......................................................... 17 9/09 rev. 0 to rev. a changes to features section ............................................................ 1 changes to static performance, relative accuracy, ad5545c parameter, table 1 ............................................................................. 3 moved esd caution .......................................................................... 5 changes to order ing guide .......................................................... 16 7/03 revision 0: initial version
data sheet ad5545/ad5555 rev. g | page 3 of 24 specifications electrical character istics v dd = 5 v 10%, i out = virtual gnd, gnd = 0 v, v ref = 10 v, t a = full operating temperature range, unless otherwise noted. table 1 . paramet er symbol conditions min typ max unit static performance 1 resolution n ad5545, 1 lsb = v ref /2 16 = 153 v when v ref = 10 v 16 bits ad5555, 1 lsb = v ref /2 14 = 610 v when v ref = 10 v 14 bits relative accuracy inl ad5545b 2 lsb ad5555c 1 lsb ad5545c 1 lsb differential nonlinearity dnl monotonic 1 lsb output leakage current i out data = 0x0000, t a = 25c 10 na data = 0x0000, t a = t a max 20 na full - scale gain error g fse data = full scale 1 4 mv full - scale temp erature coefficient 2 tcv fs 1 ppm/c reference input v ref range v ref C 12 +12 v input resistance r ref 5 k? 3 input capacitance 2 c ref 5 pf analog output output current i out data = full scale 2 ma output capacitance 2 c out code dependent 200 pf logic inputs and output logic i nput low voltage v il 0.8 v logic input high voltage v ih 2.4 v input leakage current i il 10 a input capacitance 2 c il 10 pf interface timing 2 , 4 50 mhz clock input frequency f clk 10 ns clock width high t ch 10 ns clock width low t cl 0 ns cs to clock setup t css 10 ns clock to cs hold t csh 5 ns data setup t ds 10 ns data hold t dh 5 ns ldac se tup t lds 10 ns hold t ldh 10 ns ldac width t ldac 50 mhz supply characteristics power supply range v dd range 4.5 5.5 v positive supply current i dd logic inputs = 0 v 10 a power dissipation p diss logic inputs = 0 v 0.055 mw power supply sensitivity pss ? v dd = 5% 0.006 %/%
ad5545/ad5555 data sheet rev. g | page 4 of 24 parameter symbol conditions min typ max unit ac characteristics output voltage setting time t s to 0.1% full scale, data = zero scale to full scale to zero scale 0.5 s reference multiplying bw bw v ref = 100 mv rms, data = full scale, c1 = 5.6 pf 6.9 mhz dac glitch impulse q v ref = 0 v, data = midscale minus 1 to midscale C2 nv-s feedthrough error v out /v ref data = zero scale, v ref = 100 mv rms, f = 1 khz, same channel C81 db digital feedthrough q cs = logic high and f clk = 1 mhz 7 nv-s total harmonic distortion thd v ref = 5 v p-p, data = full scale, f = 1 khz to 10 khz C104 db analog crosstalk c ta v refb = 0 v, measure v outb with v refa = 5 v p-p sine wave, data = full scale, f = 1 khz to 10 khz C95 db output spot noise voltage e n f = 1 khz, bw = 1 hz 12 nv/hz 1 all static performance tests (except i out ) are performed in a closed-loop system using an external precision op1177 i-to-v converter am plifier. the ad5545 r fb terminal is tied to the amplifier output. typical values represent average read ings measured at 25c. 2 these parameters are guaranteed by design and not subject to production testing. 3 all ac characteristic tests are perfor med in a closed-loop system using an ad8038 i-to-v converter amplifier and the ad8065 for the thd specification. 4 all input control signals are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. timing diagrams 02918-0-003 a1 sdi clk cs t css t ds t dh t ch t cl t ldac t csh t lds t ldh ldac a0 input reg ld d1 d0 d15 d14 d13 d12 d11 d10 figure 2. ad5545 18-bit data word timing diagram 02918-0-004 a1 sdi clk cs t css t ds t dh t ch t cl t ldac t csh t lds t ldh ldac a0 input reg ld d1 d0 d13 d12 d11 d10 d09 d08 figure 3. ad5555 16-bit data word timing diagram
data sheet ad5545/ad5555 rev. g | page 5 of 24 absolute maximum rat ings table 2 . parameter rating v dd to gnd C 0.3 v to +8 v v ref to gnd C 18 v to +18 v logic inputs to gnd C 0.3 v to +8 v v(i out ) to gnd C 0.3 v to v dd + 0.3 v input current to any pin except supplies 50 ma package power dissipation (t j max C t a )/ ja thermal resistance ja 16- lead tssop 150c/w maximum junction temperature (t j max) 150c operating temperature range C 40c to +85c storage temperature range C 65c to +150c lead temperature ru - 16 (vapor phase, 60 sec) 215c ru - 16 (infrared, 15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra t ing only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specific a tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5545/ad5555 data sheet rev. g | page 6 of 24 pin configuration a nd function descript ions ad5545/ ad5555 top view (not to scale) 8 7 6 5 1 4 3 2 9 10 11 12 16 13 14 15 cs dgnd clk v dd msb ldac rs sdi v ref b r fb b a gnd b i out b r fb a a gnd a i out a v ref a 0 2 9 1 8 - 0 - 0 0 2 figure 4 . 16 - le ad tssop table 3 . pin function descriptions pin o. mnemonic description 1 r fb a establish voltage output for dac a by connecting this pin to an external amplifier output. 2 v ref a dac a reference voltage input terminal. establishe s dac a full - scale output voltage. this p in can be tied to the v dd pin. 3 i out a dac a current output. 4 a gnd a dac a analog ground. 5 a gnd b dac b analog ground. 6 i out b dac b current output. 7 v ref b dac b reference voltage input terminal. establishes d ac b full - scale output voltage. this p in can be tied to the v dd pin. 8 r fb b establish voltage output for dac b by the r fb b pin connecting to an external amplifier output. 9 sdi serial data input. input data loads directly into the shift register. 10 rs reset pin, active low input. input registers and dac registers are set to all 0s or midscale. register data = 0x0000 when msb = 0. register data = 0x8000 for ad5545 and 0x2000 for ad5555 when msb = 1. 11 cs chip select , active low input. disables shift register loading when high. transfers serial register data to the input register when cs / ldac returns high. this does not affect ldac operation. 12 dgnd digital groun d pin. 13 v dd positive power supply input. specified range of operation 5 v 10%. 14 msb msb bit sets output to either 0 or midscale during a reset pulse ( rs ) or at system power - on. output equals zero scale when msb = 0 and midscale wh en msb = 1. msb pin can also be tied permanently to ground or v dd . 15 ldac load dac register strobe, level sensitive active low. transfers all input register data to dac registers. asynchronous active low input. see table 7 and table 8 for operation. 16 clk clock input. positive edge clocks data into shift register.
data sheet ad5545/ad5555 rev. g | page 7 of 24 typical performance characteristics 1.0 0.8 0.6 0 8192 16384 24576 32768 40960 49152 57344 65536 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 inl ( lsb) code ( decimal) 0 2 9 1 8 - 0 - 0 0 9 figure 5 . ad5545 integral nonlinearity error 1.0 0.8 0.6 0 8192 16384 24576 32768 40960 49152 57344 65536 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 dnl (lsb) code (decimal) 0 2 9 1 8 - 0 - 0 1 0 figure 6 . ad5545 differential nonlinearity error 1.0 0.8 0.6 0 2048 4096 6144 8192 10240 12288 14336 16384 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 inl (lsb) code (decimal) 0 2 9 1 8 - 0 - 0 1 1 figure 7 . ad5555 integral nonlinearity error 1.0 0.8 0.6 0 0248 4096 6144 8192 10240 12288 14336 16384 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 dnl (lsb) code (decimal) 0 2 9 1 8 - 0 - 0 1 2 figure 8 . ad5555 differential nonlinearity error 1.5 1.0 2 4 ge dnl inl 6 8 10 0.5 0 ? 0.5 ? 1.0 ? 1.5 linearity error (lsb) supply voltage v dd (v) v ref = 2 . 5 v t a = 2 5 c 0 2 9 1 8 - 0 - 0 1 3 figure 9 . linearity errors vs. v dd 5 4 0 0.5 1.0 1.5 2.0 3.0 3.5 2.5 4.0 4.5 5.0 3 2 1 0 supply current i dd (lsb) logic input voltage v ih (v) v dd = 5 v t a = 2 5 c 0 2 9 1 8 - 0 - 0 1 4 figure 10 . supply current vs. logic input voltage
ad5545/ad5555 data sheet rev. g | page 8 of 24 3.0 2.5 10k 100k 1m 10m 100m 2.0 1.5 1.0 0 . 5 0 supply current (ma) clock frequency (hz) 0x5555 0x8000 0xffff 0x0000 0 2 9 1 8 - 0 - 0 1 5 figure 11 . supply current vs. clock frequency 90 70 10 100 1k 10k 100k 1m 50 40 60 80 30 1 0 2 0 0 pssr (-db) frequency (hz) v dd = 5 v 10% v ref = 1 0 v 0 2 9 1 8 - 0 - 0 1 6 figure 12 . power supply rejection ratio n vs. frequency 02918-0-113 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 power spectrum (db) frequenc y (hz) 0 5 10 15 20 25 figure 13 . ad5545/ad5555 analog thd 02918-0-117 2 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 10k 100k 1m 10m 100m gain (db) frequency (hz) figure 14 . reference multiplying bandwidth 0 2 9 1 8 - 0 - 0 1 8 v out cs figure 15 . settling time 02918-0-119 ?3.70 ?4.05 ?4.00 ?3.95 ?3.90 ?3.85 ?3.80 ?3.75 ?200 400 300 200 100 0 ?100 v out (v) time (ns) figure 16 . midscale transition and digital feedthrough
data sheet ad5545/ad5555 rev. g | page 9 of 24 theory of operation the ad5545/ad5555 contain a 16 - /14 - bit, current - output, digital - to - analog converter, a serial - input register, and a dac regi s ter. both parts require a minimum of a 3 - wire serial data interface with an additional ldac for dual channel simultaneous u p date. d igital - to - analog converter the dac architecture uses a current - steering r - 2r ladder design. figure 17 sho ws the typical equivalent dac. the dac contains a matc h ing feedback resistor for use with an external i - to - v converter amplifier. the r fb pin is connected to the output of the external amplifier. the i out terminal is co n nected to the inverting input of t he external amplifier. these dacs are designed to operate with either negative or positive reference vol t ages. the v dd power pin is used only by the logic to drive the dac switches on and off . note that a matching switch is used in series with the interna l 5 k? feedback resistor. if users attempt to measure the r fb value, power must be applied to v dd to achieve continuity. the v ref input voltage and the digital data ( d ) loaded into the corresponding dac register, according to equation 1 and equation 2, det ermine the dac output vol t age. 536 , 65 / C d v v ref out = (1) 384 , 16 / C d v v ref out = (2) note that the output full - scale polarity is the opposite of the v ref polarity for dc reference voltages. v ref digital interface connections omitted for clarity: switches s1 and s2 are closed, v dd must be powered r 2r 2r 2r r 5k ? s2 s1 r r v dd r fb i out gnd 0 2 9 1 8 - 0 - 0 0 5 figure 17 . equivalent r - 2r dac circu it these dacs are also designed to accommodate ac reference inpu t signals. the ad5545/ad5555 accommodate input reference voltages in the range of C 12 v to +12 v. the reference voltage inputs exhibit a constant nomi nal input - resistance value of 5 k?, 30%. the dac output (i out ) is code depe n dent, pro - ducing various output resistances and capacitances. when choosing an external amplifier, the user should take into account the variation in impedance generated by the ad5545/ ad5555 on the amplifiers i nverting input node. the feedback resistance in parallel with the dac ladder resistance dominates output vol t age noise. v ref a digital interface connections omitted for clarity: switches s1 and s2 are closed, v dd must be powered r 2r 2r 2r r 5k ? s2 s1 +3v ? 3v r r v out v in v dd 5v 2.500v r fb a i out a a gnd a gnd 0 2 9 1 8 - 0 - 0 0 6 ad5545/ad5555 adr03 ad8628 load v out v ee v cc figure 18 . recommended system connections
ad5545/ad5555 data sheet rev. g | page 10 of 24 serial data interfac e the ad5545/ad5555 use a minimum 3 - wire ( cs , sdi, clk) serial data interface for single channel update operation. with table 7 as an example (ad5545), users can tie ldac low and rs high, and then pull cs low for an 18 - bit duration. new serial data is then clocked into the serial - input register in an 18 - bit data - word format with the msb bit loaded first. table 8 defines the truth table for the ad5555. data is placed on the sdi pin and clocked into the register on the positive clock edge of clk. for the ad5545, only the last 18 - bits clocked into the serial register are interrogated when the cs pin is strobed high, transferring the serial register data to the dac reg ister and updating the output. if the applied microco n troller outputs serial data in different lengths than the ad5545, such as 8 - bit bytes, three right justified data bytes can be written to the ad5545. the ad5545 ignore s the six msb and recognize s the 18 lsb as valid data. after loading the serial register, the rising edge of cs transfers the serial register data to the dac register and updates the output; during the cs strobe, the clk should not be to g gled. if users wa nt to program each channel separately but update them simultaneously, program ldac and rs high initia l ly, then pull cs low for an 18 - bit duration and program dac a with the proper address and data bits. cs is then pulled high to latch data to the dac a register. at this time, the output is not updated. to load dac b data, pull cs low for an 18 - bit dur a tion and program dac b with the proper address and data, then pull cs high to latch data to the dac b register. finally, pull ldac low and then high to update both the dac a and dac b outputs simultaneously. table 6 shows that each dac a and dac b can be individu ally loaded with a new data value. in addition, a common new data value can be loaded into both dacs simultaneously by setting bit a1 = a0 = high. this command enables the parallel comb i nation of both dacs, with i out a and i out b tied together, to act as one dac with significant improved noise pe r formance. esd protection circuits all logic input pins contain back - biased esd protection zeners connected to digital ground (dgnd) and v dd as shown in figure 19. v dd 0 2 9 1 8 - 0 - 0 0 7 5k ? dgnd digital inputs figure 19 . equivalent esd protection circuits table 4 . ad5545 serial input register data format, data is loaded in the msb - first format 1 msb lsb bit position b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b 2 b1 b0 data word a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the cs lines positive edge returns to logi c high. at this point, an internally generated load strobe transfers the serial register data contents (bit d15 to bit d0) to the d e coded dac input register address determined by bit a1 and bit a0. any extra bits clocked into the ad5545 shift register are ignored; only the last 18 bits clocked in are used. if double - buffered data is not needed, the ldac pin can be tied logic low to disable the dac regi s ters. table 5 . ad5555 serial input register data format, data is loaded in the msb - first format 1 msb lsb bit position b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 data word a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 note that only the last 16 bits of data clocked into the serial register (addre ss + data) are inspected when the cs lines positive edge returns to logic high. at this point, an internally generated load strobe transfers the serial register data contents (bit d1 3 to bit d0) to the d e coded dac input register addres s determined by bit a1 and bit a0. any extra bits clocked into the ad5555 shift register are ignored; only the last 16 bits c locked in are used. if double - buffered data is not needed, the ldac pin can be tied logic low to disable the dac registers. table 6 . address decode a1 a0 dac decoded 0 0 none 0 1 dac a 1 0 dac b 1 1 dac a and dac b
data sheet ad5545/ad5555 rev. g | page 11 of 24 table 7. ad5545 control logic truth table 1, 2 cs clk ldac rs msb serial shift register function input register function dac register h x h h x no effect latched latched l l h h x no effect latched latched l ? + h h x shift register data advanced one bit latched latched l h h h x no effect latched latched ? + l h h x no effect selected dac updated with current sr current latched h x l h x no effect latched transparent h x h h x no effect latched latched h x ? + h x no effect latched latched h x h l 0 no effect latched data = 0x0000 latched data = 0x0000 h x h l h no effect latched data = 0x8000 latched data = 0x8000 1 sr = shift register, ? + = positive logic transition, and x = dont care. 2 at power-on, both the input register and the dac register are loaded with all 0s. table 8. ad5555 control logic truth table 1, 2 cs clk ldac rs msb serial shift register function input register function dac register h x h h x no effect latched latched l l h h x no effect latched latched l ? + h h x shift register data advanced one bit latched latched l h h h x no effect latched latched ? + l h h x no effect selected dac updated with current sr current latched h x l h x no effect latched transparent h x h h x no effect latched latched h x ? + h x no effect latched latched h x h l 0 no effect latched data = 0x0000 latched data = 0x0000 h x h l h no effect latched data = 0x2000 latched data = 0x2000 1 sr = shift register, ? + = positive logic transition, and x = dont care. 2 at power-on, both the input register and the dac register are loaded with all 0s. power-up sequence it is recommended to power-up v dd and ground prior to any reference voltages. the ideal power-up sequence is a gnd x, dgnd, v dd , v ref x, and digital inputs. a noncompliance power-up sequence can elevate reference current, but the device will resume normal operation once v dd is powered. layout and power supply bypassing it is a good practice to employ compact, minimum lead length layout design. the input leads should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramic capacitors. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at v dd to minimize any transient disturbance and to filter any low frequency ripple (see figure 20). users should not apply switching regulators for v dd due to the power supply rejection ratio degradation over frequency. ad5545/ ad5555 v dd v dd a gnd x dgnd 02918-0-008 c1 + c2 10 ? f 0.1 ? f figure 20. power supply bypassing and gr ounding connection grounding the dgnd and a gnd x pins of the ad5545/ad5555 refer to the digital and analog ground references. to minimize the digital ground bounce, the dgnd terminal should be joined remotely at a single point to the analog ground plane (see figure 20).
ad5545/ad5555 data sheet rev. g | page 12 of 24 applications information stability ad5545/ad5555 ad8628 v ref v ref i out v o v dd v dd r fb u1 u2 c1 gnd 0 2 9 1 8 - 0 - 0 2 0 figure 21 . operational compensation capacitor for gain peaking prevention in the i - to - v configuration, the i out of the dac and the inverting node of the op amp mus t be connected as close as poss i ble, and proper pcb layout techniques must be employed. because every code change corresponds to a step function, gain peaking may occur if the op amp has limited gbp, and if there is exce s sive parasitic capacitance at the i nverting node. an optional compensation capacitor, c1, can be added for st a bility as shown in figure 21 . c1 should be found empirically, but 6 pf is generally more than adequate for the compens a tion. positive voltage out put to a ch ieve the positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resi s tors tolerance errors. to generate a negative reference, the reference can be level shifted by an op amp such that the v out and gnd pins of the reference become the virtual gr ound and ?2.5 v, r e spectively (see figure 22). ad5545/ad5555 1/2 ad8628 1/2 ad8620 adr03 v ref i out v out v in v dd gnd gnd 0 2 9 1 8 - 0 - 0 2 1 v o 0 < v o < +2.5 r fb u2 u1 +5v v+ ? 5v v ? +5v ? 2.5v u3 c1 u4 figure 22 . positive voltage output configuration bipolar output the ad5545/ad5555 is inherently a 2 - quadrant multiplying da c . it can easily be set up for u nipolar output operation. the full - scale output polarity is the inverse of the refe r ence input voltage. in some applications, it may be necessary to generate the full 4 - quadrant multiplying capability or a bipolar output swing. this is easily accomplishe d by using an additional external ampl i fier, u4, configured as a summing amplifier (see figure 23 ). in this circuit, the second amp lifier, u4, provides a gain of 2, which increases the output span ma g nitude to 5 v. biasing the ext ernal amplifier with a 2.5 v offset from the reference voltage results in a full 4 - quadrant multiplying circuit. the transfer equation of this circuit shows that both neg a tive and positive output voltages are created because the input data ( d ) is increment ed from code zero ( v out = ? 2.5 v) to mid s cale ( v out = 0 v) to full scale ( v out = +2.5 v). v out = ( d /32,768 ? 1) v ref (ad5545) (3) v out = ( d /8192 ? 1) v ref (ad5555) (4) for the ad5545, the external resistance tolerance becomes the dominant error that users should be aware of. ad5545/ad5555 1/2 ad8620 1/2 ad8620 adr03 v ref i out v out v in v dd gnd gnd 0 2 9 1 8 - 0 - 0 2 2 v o ? 2.5 < v o < +2.5 r fb u2 u3 u1 +5v +5v v+ ? 5v 5v v ? u4 c1 c2 r1 10k ? 0.01% 10k ? 0.01% 5k ? 0.01% r2 r3 figure 23 . four - quadrant multiplying application circuit
data sheet ad5545/ad5555 rev. g | page 13 of 24 programmable current source figure 24 shows a versatile v - to - i conversion circuit using improved howland current pump. in addition to the precisi on current conversion it provides, this circuit enables a bidirec - tional cu r rent flow and high voltage compliance. this circuit can be used in a 4 ma to 20 ma current transmitter wi th up to a 500 ? of load. in figure 24 , it shows that if the resistor ne t work is matched, the load current is ( ) d v r3 r1 r3 r2 i ref l + = (5) r 3, in theory, can be made small to achieve the current needed within the u3 output current driving capability. this circuit is versatile such that the ad8510 can deliver 20 ma in both d i rections, and the voltage compliance approaches 15 v, which is mainly limited by the supply voltages of u3. however, users must pay attention to the compensati on. without c1, it can be shown that the output impe d ance becomes ( ) ( ) ( ) r3 r2 1 r 3 r 2 r r1 r2 r1 r3 1 r z o + + + = C (6) if the resistors are perfectly matched, z o is infinite, which is desirable, and the resistors behave as an ideal current source. on the other hand, if they are not matched, z o can be either positive or negative. the latter can cause oscillation. as a result, c1 is needed to prevent the oscill a tion. for critical applications, c1 could be found empirically but typically falls in the range of a few p icofarads . ad5545/ad5555 ad8628 ad8510 v ref v ref i out v dd v dd v dd c1 10pf v ss load gnd 0 2 9 1 8 - 0 - 0 2 3 v l i l r fb u2 u3 u1 v+ v ? r3' 50 ? r1' 150k ? r2' 15k ? r1 150k ? r2 15k ? r3 50 ? fig ure 24 . programmable current source with bidire c tional current control and high voltage compliance capabilities
ad5545/ad5555 data sheet rev. g | page 14 of 24 dac with programmable input reference range because high voltage references can be costly, users may consider using one of the dacs, a digital potentiometer, and a low voltage reference to form a single-channel dac with a programmable input reference range. this approach optimizes the programmable range as well as facilitates future system upgrades with just software changes. figure 25 shows this implementation. v ref ab is in the feedback network, therefore, ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ??? wa wb n a ref_ab wa wb ref ref r r 2 d v r r vabv CC1 (7) where: v ref ab = reference voltage of v ref a and v ref b v ref = external reference voltage d a = dac a digital code in decimal n = number of bits of dac r wb and r wa are digital potentiometer 128-step programmable resistances and are given by ab c wb r d r 128 ? (8) ab c wa r d r 128 128 ? ? (9) c c wa wb d d r r ? ? 128 (10) where d c = digital potentiometer digital code in decimal (0 d c 127). by putting equations 7 through 10 together, the following results: c c n a c c ref ref d d d d d vabv ? ?? ? ? ? ? ? ? ? ? ? ? ?? 128 2 1 128 1 (11) table 9 shows a few examples of v ref ab of the 14-bit ad5555. table 9. v ref ab vs. d b and d c of the ad5555 d c d a v ref ab 0 x v ref 32 0 1.33 v ref 32 8192 1.6 v ref 64 0 2 v ref 64 8192 4 v ref 96 0 4 v ref 96 8192 C8 v ref the output of dac b is, therefore, n b ref ob d abvv 2 ?? (12) where d b is the dac b digital code in decimal. the accuracy of v ref ab is affected by the matching of the input and feedback resistors and, therefore, a digital potentiometer is used for u4 because of its inherent resistance matching. the ad7376 is a 30 v or 15 v, 128-step digital potentiometer. if 15 v or 7.5 v is adequate for the application, a 256-step ad5260 digital potentiometer can be used instead. ad5555 v out v in gnd 02918-0-024 v o b trim temp pot u2a u4 w ab u3 5 3 2 4 6 +5v +15v +15v v+ ?15v v? c1 c3 v ref a v ref v ref_ab i out a a gnd a v dd r fb a c2 2.2p op4177 u2b v ref b i out b a gnd b r fb b op4177 u2c op4177 adr03 ad7376 u1a u1b figure 25. dac with programmable input reference range
data sheet ad5545/ad5555 rev. g | page 15 of 24 reference selection when selecting a reference for use with the ad55xx series of current output dacs, pay attention to the output voltage, temperature coefficient specification of the reference. choosing a precision reference with a low output temperature coefficient minimizes error sources. ta ble 10 lists some of the references available from analog devices, inc., that are suitable for use with this range of current output dacs. amplifier selection the primary requirement for the current - steering mode is an amplifier with low input bias curren ts and low input offset voltage. because of the code - dependent output resistance of the dac, th e input offset voltage of an op amp is multiplied by the variable gain of the circuit. a change in this noise gain between two adjacent digital fractions produce s a step change in the output voltage due to the amplifiers input offset voltage. this output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the dac to be nonmonotonic. the input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the feedback resistor, r fb . common - mode rejection of the op amp is important in voltage - switchi ng circuits because it produces a code - dependent error at the voltage output of the circuit. provided that the dac switches are driven from true wideband low impedance sources (v in and agnd), they settle quickly. consequently, the slew rate and settling ti me of a voltage - switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configuration, minimize capacitance at the v ref node (the voltage output node in this application) of the dac. this is done by using l ow input capacitance buffer amplifiers and careful board design. analog devices offers a wide range of amplifiers for both precision dc and ac applications, as listed in table 11 and table 12. table 10 . suitable analog devices precision references part no. output voltage (v) initial tolerance (%) maximum temperature drift (ppm/c) i ss (ma) output noise (v p - p) package(s) adr01 10 0. 05 3 1 20 soic -8 adr01 10 0.05 9 1 20 tsot - 5, sc70-5 adr02 5.0 0.06 3 1 10 soic -8 adr02 5.0 0.06 9 1 10 tsot - 5, sc70-5 adr03 2.5 0.1 3 1 6 soic -8 adr03 2.5 0.1 9 1 6 tsot - 5, sc70-5 adr06 3.0 0.1 3 1 10 soic -8 adr06 3.0 0.1 9 1 10 tsot - 5, sc70-5 adr420 2.048 0.05 3 0.5 1.75 soic - 8, msop -8 adr421 2.50 0.04 3 0.5 1.75 soic - 8, msop -8 adr423 3.00 0.04 3 0.5 2 soic - 8, msop -8 adr425 5.00 0.04 3 0.5 3.4 soic - 8, msop -8 adr431 2.500 0.04 3 0.8 3.5 soic - 8, msop -8 adr435 5.000 0.04 3 0.8 8 soic - 8, msop - 8 adr391 2.5 0.16 9 0.12 5 tsot -5 adr395 5.0 0.10 9 0.12 8 tsot -5
ad5545/ad5555 data sheet rev. g | page 16 of 24 table 11. suitable analog devices precision op amps part no. supply voltage (v) v os maximum (v) i b maximum (na) 0.1 hz to 10 hz noise (v p-p) supply current (a) package(s) op97 2 to 20 25 0.1 0.5 600 soic-8 , pdip-8 op1177 2.5 to 15 60 2 0.4 500 msop-8, soic-8 ad8675 5 to 18 75 2 0.1 2300 msop-8, soic-8 ad8671 5 to 15 75 12 0.077 3000 msop-8, soic-8 ada4004-1 5 to 15 125 90 0.1 2000 soic-8, sot-23-5 ad8603 1.8 to 5 50 0.001 2.3 40 tsot-5 ad8607 1.8 to 5 50 0.001 2.3 40 msop-8, soic-8 ad8605 2.7 to 5 65 0.001 2.3 1000 wlcsp-5, sot-23-5 ad8615 2.7 to 5 65 0.001 2.4 2000 tsot-5 ad8616 2.7 to 5 65 0.001 2.4 2000 msop-8, soic-8 table 12. suitable analog devices high speed op amps part no. supply voltage (v) bw @ acl (mhz) slew rate (v/s) v os (max) (v) i b (max) (na) package(s) ad8065 5 to 24 145 180 1500 0.006 soic-8, sot-23-5 ad8066 5 to 24 145 180 1500 0.006 soic-8, msop-8 ad8021 5 to 24 490 120 1000 10,500 soic-8, msop-8 ad8038 3 to 12 350 425 3000 750 soic-8, sc70-5 ada4899-1 5 to 12 600 310 35 100 lfcsp-8, soic-8 ad8057 3 to 12 325 1000 5000 500 sot-23-5, soic-8 ad8058 3 to 12 325 850 5000 500 soic-8, msop-8 ad8061 2.7 to 8 320 650 6000 350 sot-23-5, soic-8 ad8062 2.7 to 8 320 650 6000 350 soic-8, msop-8 ad9631 3 to 6 320 1300 10,000 7000 soic-8, pdip-8
data sheet ad5545/ad5555 rev. g | page 17 of 24 evaluation board f or the ad5545 the eval - ad5545sdz is used in conjunction with an sdp1z system demonstration platform board available from analog devices, which is purchased separately from the evaluation board. the usb - to - spi communication to the a d554 5 is completed using this blackfin ? - based demonstration board. system demonstration platform the system demonstration platform (sdp) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. the sdp board is base d on the blackfin adsp - bf527 processor with usb connectivity to the pc through a usb 2.0 high speed port. for more information about this device, see the system dem onstration platform web page . operating the evalua tion board the evaluation board requires 12 v and +5 v supplies. the +12 v v dd and ? 12 v v ss are used to power the output amplifier, and the +5 v is used to power the dac (dvdd). 02918-0-025 figure 26 . evaluation board software C device selection window 02918-0-027 figure 27 . evaluation board software ad5545 dual dac
ad5545/ad5555 data sheet rev. g | page 18 of 24 evaluation board sch ematics 02918-0-028 figure 28 . eval - ad5545sdz schematic part a
data sheet ad5545/ad5555 rev. g | page 19 of 24 02918-0-029 figure 29 . eval - ad5545sdz schematic part b
ad5545/ad5555 data sheet rev. g | page 20 of 24 02918-0-030 figure 30 . eval - ad 55 45sdz schematic part b
data sheet ad5545/ad5555 rev. g | page 21 of 24 evalua tion board layout 02918-0-031 figure 31 . silkscreen 02918-0-032 figure 32 . component side
ad5545/ad5555 data sheet rev. g | page 22 of 24 02918-0-033 figure 33 . solder side
data sheet ad5545/ad5555 rev. g | page 23 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 34 . 16 - lead thin shrink small ou tline package [tssop] (ru - 16) dimensions shown in mill i meters ordering guide model 1 , 2 inl lsb dnl lsb resolution (bits) temperature range package description package option ordering qty ad5545bruz 2 1 16 ? 40c to +85c 16- lead tssop ru -16 96 ad5545b ruz - reel7 2 1 16 ? 40c to +85c 16- lead tssop ru -16 1000 ad5545cruz 1 1 16 ? 40c to +85c 16- lead tssop ru -16 96 ad5545cruz - reel7 1 1 16 ? 40c to +85c 16- lead tssop ru -16 1000 ad5555cru 1 1 14 ? 40c to +85c 16- lead tssop ru -16 96 ad5555cru -re el7 1 1 14 ? 40c to +85c 16- lead tssop ru -16 1000 ad5555cruz 1 1 14 ? 40c to +85c 16- lead tssop ru -16 96 a d 5555cruz - reel7 1 1 14 ? 40c to +85c 16- lead tssop ru -16 1000 ev - ad5544/45sdz evaluation board 1 the ad5545/ad5555 contain 3131 transistors. the die size measures 71 mil. 96 mil., 6816 sq. mil. 2 z = rohs compliant part.
ad5545/ad5555 data sheet rev. g | page 24 of 24 notes ? 2003 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02918 - 0 - 4/13(g)

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